1. Technical Field
Various aspects of the present disclosure generally relate to a semiconductor memory apparatus, and more particularly, to a circuit and a method for controlling precharge in a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus typically receives an external command and performs active and precharge operations. The semiconductor memory apparatus performs a read operation or a write operation in the active operation. In the read operation, data is outputted from memory cells, and in the write operation, data is inputted to memory cells. When one active operation is completed, charges remain in bit lines and data input/output lines on which data input and output operations have been performed. Only when these signal lines are precharged to a preset level, the next active operation can be properly performed. Therefore, the semiconductor memory apparatus has a precharge control circuit which precharges the respective signal lines between active intervals.
In a semiconductor memory apparatus, one precharge control circuit may be provided for each memory bank and is configured to generate auto precharge signals in precharge operations for read operations (hereafter referred to as “read precharge operation”) and in precharge operations for write operations (hereafter referred to as “write precharge operation”). To achieve this, the precharge control circuit may have a read precharge control unit and a write precharge control unit. The precharge control circuit generates a burst clock signal using an internal clock signal and generates a read auto precharge signal through the read precharge control unit by using the burst clock signal and burst length information in a read operation. The precharge control circuit generates a write auto precharge signal through the write precharge control unit by using the burst clock signal, the burst length information, and write latency information in a write operation. The precharge control circuit may combine the read auto precharge signal, the write auto precharge signal, and bank information to generate an auto precharge signal, and transmits the generated auto precharge signal to a corresponding memory bank.
FIG. 1 shows waveforms of a read write mode signal rdwt which distinguishes a read operation and a write operation, a data input off signal dioff which indicates an interval during which data is not inputted, and a burst clock signal bclk. The read write mode signal rdwt indicates a read operation mode at a low level and a write operation mode at a high level. The data input off signal dioff is enabled to a high level during an interval in which data is not inputted to the memory bank, that is, in an all bank idle mode or a refresh mode. The burst clock signal bclk is a clock signal that is inputted to the read precharge control unit and the write precharge control unit.
During an interval in which the read write mode signal rdwt has a low level, that is, in the read operation mode, the write precharge control unit need not be activated. Also, the write precharge control unit need not be activated during an interval in which the data input off signal dioff is enabled since a data input operation is not actually performed during that time. As shown in the drawing, however, the burst clock signal bclk is implemented to constantly toggle and such constant toggling configuration makes the activated burst clock signal bclk resulting from such constant toggling implementation makes the write precharge control unit be activated as well.
In this way, the precharge control circuit of a related art semiconductor memory apparatus is configured such that the write precharge control unit is activated even under situations where a write operation mode is not performed, thereby increasing power consumption. In addition, since precharge control circuits are provided in a number corresponding to the number of memory banks, the increased power consumption lowers power utilization efficiency of the entire semiconductor memory apparatus. In order to reduce power consumption in a semiconductor memory apparatus, it is necessary to reduce meaningless current flow in the precharge control circuit. For this reason, a novel technical solution for reducing power consumption is needed in the art.